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| author | Bunnaroath Sou <35707615+bsousi5@users.noreply.github.com> | 2019-03-06 13:49:16 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-06 13:49:16 -0800 |
| commit | 90ab2c8561eb532b382206c8bf3ec1af74f18257 (patch) | |
| tree | b803291867d6e05146af113c8a8210bf83009528 /bsp/coreip-e76-arty/README.md | |
| parent | 87f176dfbbbf1a64bd3e034713434393a0f3518b (diff) | |
| parent | 51dde8b98faf94da540624b9c7bb7fffa69daee9 (diff) | |
Merge pull request #194 from sifive/arty-19.2
Add E76, S76 arty targets for all 19.2 CoreIPs release
Diffstat (limited to 'bsp/coreip-e76-arty/README.md')
| -rw-r--r-- | bsp/coreip-e76-arty/README.md | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/bsp/coreip-e76-arty/README.md b/bsp/coreip-e76-arty/README.md new file mode 100644 index 0000000..3dddb18 --- /dev/null +++ b/bsp/coreip-e76-arty/README.md @@ -0,0 +1,16 @@ +The SiFive E76 Standard Core is a high-performance 32-bit embedded processor which is fully-compliant with the RISC-V ISA. Its advanced memory subsystem enables inclusion of tightly-integrated memory and caches. + +The E76 is ideal for applications which require high performance -- but have power constraints (e.g., Augmented Reality and Virtual Reality , IoT Edge Compute, Biometric Signal Processing, and Industrial Automation). + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAFC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches |