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| author | Bunnaroath Sou <bsou@sifive.com> | 2019-03-01 19:09:27 -0800 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-03-01 19:09:27 -0800 |
| commit | e7a3c3a2999a7b1ffbab96b5bc83061ca6f387d3 (patch) | |
| tree | d087b43efce3f2fd2483a86743d081bca3c8371d /bsp/coreip-s51/README.md | |
| parent | d546fffdae400e6bf86e5f0304f412ff2ca6a641 (diff) | |
Add CoreIPs E76, S76 for 19.2 rel
Diffstat (limited to 'bsp/coreip-s51/README.md')
| -rw-r--r-- | bsp/coreip-s51/README.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md index 60f75bf..bf808d1 100644 --- a/bsp/coreip-s51/README.md +++ b/bsp/coreip-s51/README.md @@ -6,4 +6,4 @@ This core target is suitable with Verilog RTL for verification and running appli - 4 hardware breakpoints - Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices -- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |