diff options
| author | Bunnaroath Sou <bsou@sifive.com> | 2019-03-01 19:09:27 -0800 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-03-01 19:09:27 -0800 |
| commit | e7a3c3a2999a7b1ffbab96b5bc83061ca6f387d3 (patch) | |
| tree | d087b43efce3f2fd2483a86743d081bca3c8371d /bsp/coreip-s76/README.md | |
| parent | d546fffdae400e6bf86e5f0304f412ff2ca6a641 (diff) | |
Add CoreIPs E76, S76 for 19.2 rel
Diffstat (limited to 'bsp/coreip-s76/README.md')
| -rw-r--r-- | bsp/coreip-s76/README.md | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/bsp/coreip-s76/README.md b/bsp/coreip-s76/README.md new file mode 100644 index 0000000..9623a83 --- /dev/null +++ b/bsp/coreip-s76/README.md @@ -0,0 +1,11 @@ +The SiFive S76 Standard Core is a high-performance 64-bit embedded processor which is fully-compliant with the RISC-V ISA. + +The S76 is ideal for latency-sensitive applications in domains such as storage and networking that require 64-bit memory addressability (e.g. In-storage Compute, Edge Compute, 5G Modems, Object storage etc.) + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV64IMAFDC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |