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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-04-30 16:59:29 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-30 16:59:29 +0000 |
| commit | 0c75c6a612a1620bf1ffe82cd5c77ef9a8369045 (patch) | |
| tree | 1a11e4304b06fbee9c0e525d81c0789530dfba35 /bsp/coreip-u54-rtl/README.md | |
| parent | a351dc8d6aaf1a10be9a08e66c78c37126833d6a (diff) | |
| parent | 8cd756c200cb13c036115a4b851b94f686cf3a3a (diff) | |
Merge pull request #235 from sifive/u54-rtl
Add Multicore Support
Diffstat (limited to 'bsp/coreip-u54-rtl/README.md')
| -rw-r--r-- | bsp/coreip-u54-rtl/README.md | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/bsp/coreip-u54-rtl/README.md b/bsp/coreip-u54-rtl/README.md new file mode 100644 index 0000000..cd34149 --- /dev/null +++ b/bsp/coreip-u54-rtl/README.md @@ -0,0 +1,17 @@ +The SiFive U54 Standard Core is a single-core instantiation of the world’s first RISC-V application processor, capable of supporting full-featured operating systems such as Linux. + +The U54 is ideal for low-cost Linux applications such as IoT nodes and gateways, point-of-sale, and networking. + +This target features: + +- 1 RV64GC U54 Application Core +- 16KB L1 I-cache with ECC +- 16KB L1 D-cache with ECC +- 8 Region Physical Memory Protection +- 48 Local Interrupts per core +- Sv39 Virtual Memory support with 38 Physical Address bits +- Integrated 128KB L2 Cache with ECC +- Real-time capabilities +- CLINT for multi-core timer and software interrupts +- PLIC with support for up to 128 interrupts with 7 priority levels +- Debug with instruction trace |