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| author | hsiang-chia.huang <hsiangchia.huang@sifive.com> | 2019-05-24 10:22:08 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-24 10:22:08 +0800 |
| commit | faf58a49c3b6421107ada0e8af43170a5ffafcea (patch) | |
| tree | 3996d52a748ae2420b5c9c6c9efe4158d5dece53 /bsp/sifive-hifive-unleashed/design.dts | |
| parent | 7817c5e85cb6f9f6d5b98f6702fa4b7d1fb99e02 (diff) | |
| parent | 2c0269905929128bd0bd13a55ae3d8afd60a1af6 (diff) | |
Merge branch 'development-19.05' into dhrystone_19.05
Diffstat (limited to 'bsp/sifive-hifive-unleashed/design.dts')
| -rw-r--r-- | bsp/sifive-hifive-unleashed/design.dts | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/bsp/sifive-hifive-unleashed/design.dts b/bsp/sifive-hifive-unleashed/design.dts index ee6897f..8702be3 100644 --- a/bsp/sifive-hifive-unleashed/design.dts +++ b/bsp/sifive-hifive-unleashed/design.dts @@ -33,6 +33,7 @@ next-level-cache = <&L24 &L0>; reg = <0>; riscv,isa = "rv64imac"; + riscv,pmpregions = <8>; sifive,dtim = <&L8>; sifive,itim = <&L7>; status = "okay"; @@ -60,6 +61,7 @@ next-level-cache = <&L24 &L0>; reg = <1>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L11>; status = "okay"; tlb-split; @@ -87,6 +89,7 @@ next-level-cache = <&L24 &L0>; reg = <2>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L14>; status = "okay"; tlb-split; @@ -114,6 +117,7 @@ next-level-cache = <&L24 &L0>; reg = <3>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L17>; status = "okay"; tlb-split; @@ -141,6 +145,7 @@ next-level-cache = <&L24 &L0>; reg = <4>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L20>; status = "okay"; tlb-split; @@ -160,10 +165,6 @@ #size-cells = <2>; compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <1>; - }; refclk: refclk { #clock-cells = <0>; compatible = "fixed-clock"; |