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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-04-30 16:59:29 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-30 16:59:29 +0000 |
| commit | 0c75c6a612a1620bf1ffe82cd5c77ef9a8369045 (patch) | |
| tree | 1a11e4304b06fbee9c0e525d81c0789530dfba35 /bsp/sifive-hifive-unleashed/openocd.cfg | |
| parent | a351dc8d6aaf1a10be9a08e66c78c37126833d6a (diff) | |
| parent | 8cd756c200cb13c036115a4b851b94f686cf3a3a (diff) | |
Merge pull request #235 from sifive/u54-rtl
Add Multicore Support
Diffstat (limited to 'bsp/sifive-hifive-unleashed/openocd.cfg')
| -rw-r--r-- | bsp/sifive-hifive-unleashed/openocd.cfg | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/bsp/sifive-hifive-unleashed/openocd.cfg b/bsp/sifive-hifive-unleashed/openocd.cfg new file mode 100644 index 0000000..7589897 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/openocd.cfg @@ -0,0 +1,24 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME 0x10040000 +init +halt + +# Uncomment this if you want to be able to clobber your SPI Flash, which +# probably you don't since you can do it through Linux + +# flash protect 0 0 last off |