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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-05 23:44:22 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-05 23:44:22 +0000 |
| commit | 3e51e0289ec728b6ff6dcf90bb8ddcb50c24cb04 (patch) | |
| tree | 722614f1613432a0aeb440fa0000bd4356dcbd2e /bsp/sifive-hifive1-revb/README.md | |
| parent | 39ea32d9f14d786d8457ef2e30b0bceb2e5729ce (diff) | |
| parent | 32ca53e7340922b1fa0aa379788430004504a2de (diff) | |
Merge pull request #188 from sifive/hifive1-revb
Add HiFive1 RevB Support
Diffstat (limited to 'bsp/sifive-hifive1-revb/README.md')
| -rw-r--r-- | bsp/sifive-hifive1-revb/README.md | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/bsp/sifive-hifive1-revb/README.md b/bsp/sifive-hifive1-revb/README.md new file mode 100644 index 0000000..0cc2af3 --- /dev/null +++ b/bsp/sifive-hifive1-revb/README.md @@ -0,0 +1,13 @@ +HiFive1 Rev B is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications. + +This target is ideal for getting familiarize with RISC-V ISA instructions set and freedom-metal libraries. It supports: + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 1 RGB LEDS |