From 43c3d481f420f929de1e05dfe7169edd1dbe110b Mon Sep 17 00:00:00 2001 From: cgsfv Date: Wed, 5 Jun 2019 23:26:40 +0200 Subject: Adding QEMU BSP's for E31 and S51 targets --- bsp/qemu-sifive-s51/README.md | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 bsp/qemu-sifive-s51/README.md (limited to 'bsp/qemu-sifive-s51/README.md') diff --git a/bsp/qemu-sifive-s51/README.md b/bsp/qemu-sifive-s51/README.md new file mode 100644 index 0000000..64593f3 --- /dev/null +++ b/bsp/qemu-sifive-s51/README.md @@ -0,0 +1,12 @@ +SiFive QEMU S51 is a virtual development platform matching the Freedom S510. It’s the best way to start prototyping and developing your RISC‑V applications. + +This target is ideal for getting familiarize with RISC-V ISA instructions set and freedom-metal libraries. It supports: + +- 1 hart with RV64IMAC core +- 4 hardware breakpoints +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 1 RGB LEDS -- cgit v1.2.3 From 7ad24f2558984dcf03cf58b6fc90431067e78901 Mon Sep 17 00:00:00 2001 From: cgsfv Date: Thu, 13 Jun 2019 20:36:29 +0200 Subject: Adding ref to matching QEMU repo --- bsp/qemu-sifive-s51/README.md | 2 ++ 1 file changed, 2 insertions(+) (limited to 'bsp/qemu-sifive-s51/README.md') diff --git a/bsp/qemu-sifive-s51/README.md b/bsp/qemu-sifive-s51/README.md index 64593f3..7825a98 100644 --- a/bsp/qemu-sifive-s51/README.md +++ b/bsp/qemu-sifive-s51/README.md @@ -10,3 +10,5 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an - SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 1 RGB LEDS + +This BSP matches the QEMU code in https://github.com/sifive/riscv-qemu/tree/riscv-qemu-3.1 -- cgit v1.2.3