From bc41a2c70d97bc7dd685d3f29c70a389aa38ea8b Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 5 Mar 2019 12:53:56 -0800 Subject: Add HiFive1 Rev B Signed-off-by: Nathaniel Graff --- bsp/sifive-hifive1-revb/settings.mk | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 bsp/sifive-hifive1-revb/settings.mk (limited to 'bsp/sifive-hifive1-revb/settings.mk') diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk new file mode 100644 index 0000000..fd73559 --- /dev/null +++ b/bsp/sifive-hifive1-revb/settings.mk @@ -0,0 +1,3 @@ +RISCV_ARCH = rv32imac +RISCV_ABI = ilp32 +RISCV_CMODEL = medlow -- cgit v1.2.3 From 32ca53e7340922b1fa0aa379788430004504a2de Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 5 Mar 2019 13:01:34 -0800 Subject: Generate .hex for HiFive1 RevB Set COREIP_MEM_WIDTH to cause the build system to generate a .hex file. Signed-off-by: Nathaniel Graff --- bsp/sifive-hifive1-revb/settings.mk | 1 + 1 file changed, 1 insertion(+) (limited to 'bsp/sifive-hifive1-revb/settings.mk') diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk index fd73559..d84238b 100644 --- a/bsp/sifive-hifive1-revb/settings.mk +++ b/bsp/sifive-hifive1-revb/settings.mk @@ -1,3 +1,4 @@ RISCV_ARCH = rv32imac RISCV_ABI = ilp32 RISCV_CMODEL = medlow +COREIP_MEM_WIDTH = 32 -- cgit v1.2.3